1. Field of the Invention
The present invention relates to a semiconductor chip with test pads and a tape carrier package using the same.
2. Description of the Related Art
A process for manufacturing a semiconductor device is generally divided into two processes, i.e., a wafer fabrication and a package assembly. Devices such as transistors, resistors or capacitors are integrated in a semiconductor wafer by the wafer fabrication process to form circuits having a particular predetermined function. The semiconductor wafer is divided into a plurality of individual semiconductor chips by the package assembly process. Each semiconductor chip can be provided as a chip per se, or as a final product in which it is packaged in a suitable form. A test process is performed on the semiconductor device during or after its manufacture. The test process monitors the performance of the semiconductor devices manufacturing method, and tests the quality of these devices. The testing process improves the operational reliability of the devices.
Each chip of the semiconductor wafer includes test pads for use in the test process on the wafer. The test pads may provide an electrical path to a selected circuit and allow an electrical parameter of the semiconductor device to be measured through a test probe of an external test apparatus. Tests which use the test pads may allow verification of the reliability of the integrated circuits and test the performance of the semiconductor device manufacturing method by comparing measured parameters with designed parameters.
The test pads should be of a size which is large enough to accommodate a test probe. The test pads may be formed in a main circuit area, or an area between the chips, in order to promote maximum usage of an available wafer area. In case a semiconductor chip is to be used for operating a display, the test pads may not be provided in the area between the chips, but are instead located in the semiconductor chip itself.
Referring to FIG. 1 through FIG. 2c, the conventional semiconductor chip 210 has an active surface and a back surface. The active surface has a main circuit area 211 and a peripheral area 212. Integrated circuits (not shown) are formed in the main circuit area 211. The semiconductor chip 210 is an edge-pad-type chip, in which chip pads 213 are disposed along the edges of its active surface. The chip pads 213 are connected to the integrated circuits for external input and output. The chip pads 213 are arranged in the peripheral area 212 in rows parallel to the adjacent edges of the semiconductor chip 210. Dummy pads 215 are formed in the rows of the chip pads 213 for improved connection strength during chip mounting. The dummy pads 215 assume the configuration of a chip pad, but are not connected to the integrated circuits or the chip pads 213.
A plurality of test pads 217 are connected to the integrated circuits by wirings 218 in the main circuit area 211. They are grouped together. Each test pad 217 has a size large enough to be contacted with a test probe of an external test apparatus. Although FIG. 2a and FIG. 2b show ten test pads 217 which are illustratively grouped together, the number of test pads 217 are not limited to the exemplary number depicted.
Conventionally, the test pads are connected to the integrated circuits and formed inside the chip. Thus, the circuit characteristics of the chip can be tested by making contact with the test probe of the external test apparatus on the wafer during or after the wafer fabrication process. For example, after the wafer fabrication process, an electric die sorting test may be performed to determine the electrical characteristics of the chip, i.e., whether the chip is acceptable or faulty.
The conventional semiconductor chip has some disadvantages. For example, because the test pads are formed for testing the wafer, they are not useful after the testing process has been completed. The test pads in a final product unnecessarily occupy the space on the semiconductor chip. This may be an obstacle to reduction of the chip size. Further, the test pads are located in the main circuit area. The test pads may make contact with the test probe causing damage to the integrated circuits. In order to overcome this disadvantage, a membrane should be added.
In another case, even though the test pads are formed in the area between the chips, it is difficult to significantly reduce the overall chip size.